1. Field of the Invention
Example embodiments of the present invention relate generally to an output buffer and method thereof, and more particularly to an output buffer outputting an output signal with an improved slew rate and method thereof.
2. Description of the Related Art
A Liquid Crystal Display (LCD) may include a liquid crystal panel and a driving unit. The liquid crystal panel may include a lower glass substrate on which pixel electrodes and thin film transistors may be arranged in a matrix form, an upper glass substrate on which common electrodes and a color filter layer may be formed and a liquid crystal layer disposed between the lower and upper glass substrates.
The driving unit may include an image signal processor, a controller, a gate driver and a source driver. The image signal processor may process an image signal (e.g., received from an external source) and may output a complex synchronization signal. The controller may receive the complex synchronization signal from the image signal processor and may output a horizontal synchronization signal and a vertical synchronization signal. The controller may control a timing of the synchronization signals in accordance with a mode selection signal. The gate driver and the source driver may sequentially apply a driving voltage to scanning lines and signal lines of the liquid crystal panel in response to an output signal from the controller.
In conventional LCDs, offsets between channels of a source driver may influence characteristics of the LCD. The channel offsets of the source driver may be caused by output buffers which may be included in the source driver.
FIG. 1 is a block diagram of a conventional LCD 100. Referring to FIG. 1, the LCD 100 may include a liquid crystal panel 30 on which a plurality of pixels may be respectively disposed at intersections of a plurality of gate lines GL and a plurality of source lines SL, a source driver 20 which may output image signals to the respective pixels via the source lines SL of the liquid crystal panel 30 and a gate driver 10 which may select at least one of the plurality of gate lines GL of the liquid crystal panel 30 and may turn on corresponding pixels.
Each of the plurality of pixels may include a thin film transistor TR with a gate connected to one of the plurality of gate lines GL and a drain connected to one of the plurality of source lines SL, a storage capacitor Cs connected in parallel with the source of the thin film transistor TR and a liquid crystal capacitor Clc.
FIG. 2 is a block diagram of the source driver 20 of FIG. 1. The source driver 20 of FIG. 2 may include a shift register 40, a latch 50, a data latch 60, a digital-to-analog (D/A) converter 70 and an output buffer 80.
If digital R, G, B (e.g., red, green and blue, respectively) data is received by the source driver 20, pixel information in the digital R, G, B data may be sampled for each column line by the latch 50 and may be stored in the latch 50 in response to a latch enable signal (not shown) output from the shift register 40. The data latch 60 may receive and store the digital R, G, B data sampled by the latch 50 in response to a clock signal. The D/A converter 70 may convert the digital R, G, B data stored in the data latch 60 into analog R, G, B data and may output the analog R, G, B data to the output buffer 80. The output buffer 80 may amplify a signal corresponding to the analog R, G, B data and may output the amplified signal to a corresponding source line SL of the liquid crystal panel 30 of FIG. 1.
The conventional output buffer 80 may use a supply voltage VDD as a driving voltage and the output signal of the output buffer 80 may be inverted (e.g., from positive to negative, from negative to positive, etc.) for each horizontal period, based on a common voltage Vcom, where the common voltage Vcom may equal half of the supply voltage VDD.
Channel offsets may be generated by a voltage follower amplifier (not shown) included in the output buffer 80, which may thereby cause a voltage deviation in the output signal of output buffer 80. The voltage deviation of the output signal may cause picture quality deterioration, such as stripe patterns on a screen of the liquid crystal panel 30.
In order to reduce the voltage deviation of the output signal, a chopping method may be employed. The chopping method may include dividing a voltage follower amplifier into a first part for controlling a higher voltage portion of the output signal and a second part for controlling a lower voltage portion of the output signal. By handling the higher and lower voltage portions separately with the chopping method, a size of a circuit may be reduced as compared with using a voltage follower amplifier with a rail-to-rail structure. The chopping method may decrease a slew rate of the output signal, where the slew rate may refer to a rate of which the output signal may follow an input signal. Higher slew rates may reduce response times of the LCD.
FIG. 3 is a circuit diagram of a higher voltage portion of a conventional voltage follower output buffer 300. Referring to FIG. 3, the voltage follower output buffer 300 may include a differential amplifier 310 and an output portion 320. The operation of the voltage follower output buffer 300 shown in FIG. 3 is well known to those skilled in the art, and further description is omitted for the sake of brevity.
FIG. 4 is a graph illustrating an input signal 90 and an output signal 92 of the higher voltage portion of the voltage follower output buffer 300 of FIG. 3.
Referring to FIGS. 3 and 4, during a pull-up operation in which the input signal 90 may transition to a first logic level (e.g., a higher logic level), the slew rate of the output signal 92 may be higher (e.g., the waveform of the output signal 92 may approximate the waveform of the input signal 90). However, during a pull-down operation where the input signal 90 may transition to a second logic level (e.g., a lower logic level), a gate input of an NMOS transistor NTR connected to an output terminal OUTPUT may be fixed to a constant bias voltage BIAS1.
Accordingly, since the NMOS transistor NTR may be slightly turned on by the constant bias voltage BIAS1, the NMOS transistor NTR may not quickly discharge charges accumulated in a load capacitor of a liquid crystal panel (not shown) (e.g., liquid crystal panel 30) connected to the output terminal OUTPUT. Thus, when the input signal 90 transitions to the second logic level, the slew rate of the output signal 92 may decrease as illustrated in FIG. 4.
FIG. 5 is a circuit diagram of a lower voltage portion of a conventional voltage follower output buffer 500. Referring to FIG. 5, the voltage follower output buffer 500 may include a differential amplifier 510 and an output portion 520. The operation of the voltage follower output buffer 500 shown in FIG. 3 is well known to those skilled in the art, and further description is omitted for the sake of brevity.
FIG. 6 is a graph illustrating an input signal 94 and an output signal 96 of the lower voltage portion of the voltage follower output buffer 500 of FIG. 5.
Referring to FIGS. 5 and 6, during a pull-down operation in which the input signal 94 may transition to the second logic level (e.g., a lower logic level), the slew rate of the output signal 96 may be higher (e.g., the waveform of the output signal 96 may approximate the waveform of the input signal 94). However, during a pull-up operation where the input signal 94 may transition to the first logic level (e.g., a higher logic level), a gate input of an PMOS transistor PTR connected to an output terminal OUTPUT may be fixed to the constant bias voltage BIAS1, thereby decreasing the slew rate of the output signal 96 as illustrated in FIG. 6.